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LCK4801 Datasheet

  • LCK4801

  • Low-Voltage HSTL Differential Clock

  • 10頁

  • AGERE

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Preliminary Data Sheet
July 2001
LCK4801
Low-Voltage HSTL Differential Clock
General
The LCK4801 is a low-voltage, 3.3 V HSTL
differential clock synthesizer. The LCK4801 supports
two differential HSTL output pairs with frequencies
from 336 MHz to 1 GHz. The clock is designed to
support single and multiple processor systems that
require HSTL differential inputs. The LCK4801
contains a fully integrated PLL (phase-locked loop)
which multiplies the HSTL_CLK or PECL_CLK input
frequency to match individual processor clock
frequencies. The PLL can be bypassed so that the
PCLK outputs are fed from the HSTL_CLK or
PECL_CLK input for test purposes. All outputs are
powered from a 2 V external supply to reduce on-
chip power consumption. All outputs are HSTL. The
PLL can operate in the internal feedback mode, or in
the external feedback mode for board level
debugging applications.
Features
s
s
s
s
s
s
Two fully selectable clock inputs.
Fully integrated PLL.
336 MHz to 1 GHz output frequencies.
HSTL outputs.
HSTL and LVPECL reference clocks.
32-pin TQFP package.
Description
PCLK0_EN (PULL-UP)
PCLK1_EN (PULL-UP)
TESTM (PULL-UP)
PLLREF_EN (PULL-UP)
REF_SEL (PULL-UP)
1
HSTL_CLK (PULL-UP)
HSTL_CLK (PULL-UP)
PECL_CLK (PULL-UP)
PECL_CLK (PULL-UP)
(PULL-UP)
EXTFB_IN (HSTL)
(PULL-DOWN)
EXTFB_EN (PULL-UP)
EXTFB_OUT (HSTL)
SEL[4:0] (PULL-UP)
RESET (PULL-UP)
PLL_BYPASS (PULL-UP)
2274.a (F)
0
0
/M
1
0
1
/N
PLL
0
1
PCLK0
PCLK0 (HSTL)
PCLK1
PCLK1 (HSTL)
EXTFB_OUT
DECODE
Figure 1. LCK4801 Logic Diagram

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