音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

LCK4993 Datasheet

  • LCK4993

  • Agere Systems [Low-Voltage PLL Clock Drivers]

  • AGERE

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

Data Sheet, Revision 1
May 5, 2004
LCK4993/LCK4994
Low-Voltage PLL Clock Drivers
1 Features
s
2 Description
The LCK4993 and LCK4994 low-voltage PLL clock drivers
offer user-selectable control over system clock functions.
The multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
Each of the eighteen configurable outputs drive terminated
transmission lines with impedances as low as 50
鈩?/div>
while
delivering minimal and specified output skews at LVTTL
levels. The outputs are arranged in five banks. Banks 1鈥?
allow a divide function of 1 to 12, while simultaneously
allowing phase adjustments in 625 ps鈥?300 ps increments
up to 10.4 ns. One of the output banks also includes an
independent clock invert function. The feedback bank
consists of two outputs that allow divide-by functionality
from 1 to 12 and limited phase adjustments. Any one of
these eighteen outputs can be connected to the feedback
input or drive other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change over to the secondary clock source
when the primary clock source is not in operation. The
reference inputs and feedback inputs are configurable to
accommodate both LVTTL or differential (LVPECL) inputs.
The completely integrated PLL reduces jitter and simplifies
board layout.
12 MHz鈥?00 MHz (LCK4993), or 24 MHz鈥?00 MHz
(LCK4994) output operation
Matched pair output skew <200 ps
Zero input-to-output delay
18 LVTTL 50% duty-cycle outputs capable of driving
50
鈩?/div>
terminated lines
3.3 V/2.5 V LVTTL/LV differential (LVPECL) fault tolerant
and hot insertable reference inputs
Phase adjustments from 625 ps up to 1300 ps steps up
to 鹵10.4 ns
Output divide ratios of (1鈥?, 8, 10, 12)
Multiply ratios of (1鈥?, 8) x input frequency
Individual output bank disable for aggressive power
management and EMI reduction
Output high-impedance (HI-Z) option for testing
purposes
Fully integrated PLL with lock indicator
Single 3.3 V/2.5 V 鹵 10% supply
100-pin TQFP package
100-ball FSBGA package
Pin-for-pin compatible with
CYPRESS
廬
CY7B993V and
CY7B994V
s
s
s
s
s
s
s
s
s
s
s
s
s
s

LCK4993 PDF文件相關(guān)型號(hào)

LCK4994KB-DB,LCK4994KB-DT

LCK4993相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！