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LCK4973 Datasheet

  • LCK4973

  • Agere Systems [Low-Voltage PLL Clock Driver]

  • AGERE

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Data Sheet
February 2003
LCK4973
Low-Voltage PLL Clock Driver
Features
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Description
Agere Systems鈥?LCK4973 is a 3.3 V/2.5 V,
PLL-based clock driver for high-performance RISC or
CISC processor-based systems. The LCK4973 has
output frequencies of up to 240 MHz and skews of
less than 250 ps, making it ideal for synchronous
systems. The LCK4973 contains 12 low-skew
outputs and a feedback/sync output for flexibility and
simple implementation.
There is a robust level of frequency programmability
between the 12 low-skew outputs in addition to the
input/output relationships. This allows for very
flexible programming of the input reference versus
the output frequency. The LCK4973 contains a
flexible output enable and disable scheme. This
helps execute system debug as well as offer multiple
powerdown schemes, which meet green-class
machine requirements.
The LCK4973 features a power-on reset function,
which automatically resets the device on powerup,
providing automatic synchronization between QFB
and other outputs.
The LCK4973 is 3.3 V/2.5 V compatible and requires
no external loop filters. It has the capability of driving
50
鈩?/div>
transmission lines. Series terminated lines have
the ability of driving two 50
鈩?/div>
lines in parallel,
effectively doubling the fanout.
Fully integrated PLL.
Output frequency up to 240 MHz.
Compatible with
PowerPC
廬
and
Pentium
廬
microprocessors.
52-pin TQFPT.
3.3 V/2.5 V power supply.
Pin compatible with 973 type devices.
鹵100 ps typical cycle-to-cycle jitter.
Output skews of less than 250 ps.
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