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IDT74ALVCH162721 Datasheet

  • IDT74ALVCH162721

  • 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD

  • 78.94KB

  • IDT

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IDT74ALVCH162721
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
IDT74ALVCH162721
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
鈥?0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
鈥?Extended commercial range of 鈥?40擄C to + 85擄C
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?V
CC
= 2.5V 鹵 0.2V
鈥?CMOS power levels (0.4碌 W typ. static)
鈥?Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH162721:
鈥?Balanced Output Drivers: 鹵12mA
鈥?Low switching noise
鈥?/div>
鈥?/div>
鈥?/div>
DESCRIPTION:
This 20-bit flip-flop is built using advanced dual metal CMOS technol-
ogy. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type
flip-flops with qualified clock storage. On the positive transition of the
clock (CLK) input, the device provides true data at the Q outputs if the
clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 20 outputs in either a
normal logic state (high or low) or a high-impedance state. In the high-
impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup compo-
nents. OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in the
high-impedance state.
The ALVCH162721 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive 鹵12mA at the designated threshold
levels.
The ALVCH162721 has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistor.
APPLICATIONS:
鈥?/div>
3.3V High Speed Systems
鈥?/div>
3.3V and lower voltage computing systems
Functional Block Diagram
1
OE
CLK
56
CLKEN
29
CE
C1
2
Q
1
D
1
55
1D
To 19 Other Channels
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4566/-

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