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HIGH-SPEED

16K x 16 DUAL-PORT

STATIC RAM WITH INTERRUPT

Features

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

鈥?Commercial: 15/20/25/35/55ns (max.)

鈥?Industrial 20/25/35/55ns (max.)

Low-power operation

鈥?IDT70261S

Active: 750mW (typ.)

Standby: 5mW (typ.)

鈥?IDT70261L

Active: 750mW (typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT70261S/L

x

x

x

x

x

x

x

x

x

x

x

x

x

IDT70261 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for

BUSY

output flag on Master,

M/S = L for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (鹵10%) power supply

Available in 100-pin Thin Quad Flatpack

Industrial temperature range (-40

O

C to +85

O

C) is available

for selected speeds

Functional Block Diagram

R/W

L

UB

L

R/W

R

UB

R

LB

L

CE

L

OE

L

LB

R

CE

R

OE

R

I/O

8L

-I/O

15L

I/O

0L

-I/O

7L

BUSY

L

(1,2)

I/O

Control

I/O

Control

I/O

8R

-I/O

15R

I/O

0R

-I/O

7R

BUSY

R(1,2)

A

13L

A

0L

Address

Decoder

14

MEMORY

ARRAY

14

Address

Decoder

A

13R

A

0R

CE

L

OE

L

R/

W

L

SEM

L

INT

L (2)

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

2.

BUSY

and

INT

outputs are non-tri-stated push-pull.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

R

OE

R

R/

W

R

SEM

R

INT

R(2)

3039 drw 01

M/

S

FEBRUARY 2000

1

漏2000 Integrated Device Technology, Inc.

DSC 3039/8

next

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