鈥?/div>
Microprocessor interface control logic
EFA
,
FFA
,
AEA
, and
AFA
flags synchronized by CLKA
EFB
,
FFB
,
AEB
, and
AFB
flags synchronized by CLKB
Passive parity checking on each port
Parity generation can be selected for each port
Low-power advanced BiCMOS technology
Supports clock frequencies up to 67 MHz
Fast access times of 10 ns
Available in 132-pin plastic quad flat package (PQF) or
space-saving 120-pin thin quad flat package (TQFP)
鈥?Industrial temperature range (-40擄C to +85擄C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
CLKA
W/
R
A
ENA
MBA
CSA
Port-A
Control
Logic
Mail 1
Register
Parity
Gen/Check
MBF1
PEFB
PGB
Byte Matching &
Byte Swapping
Parity
Generation
Input
Register
RST
EVEN
ODD/
64 x 36
SRAM
Output
Register
36
Device
Control
Write
Pointer
Read
Pointer
FFA
AFA
FS0
FS1
A
0
- A
35
Status Flag
Logic
36
FIFO1
Programmable Flag
Offset Register
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
EFB
AEB
B
0
-B
35
EFA
AEA
FFB
AFB
36
Bus Matching &
Byte Swapping
Parity
Generation
Output
Register
64 x 36
SRAM
PGA
Parity
Gen/Check
Mail 2
Register
PEFA
MBF2
Input
Register
Port-B
Control
Logic
CLKB
CSB
W/
R
B
BE
ENB
SIZ0
SIZ1
SW0
SW1
3146 drw 01
The IDT logo is a registered trademark and SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
漏1997
Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3146/4
1