HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT70V07S/L
FEATURES:
鈥?True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
鈥?High-speed access
鈥?Commercial: 25/35/55ns (max.)
鈥?Low-power operation
鈥?IDT70V07S
Active: 450mW (typ.)
Standby: 5mW (typ.)
鈥?IDT70V07L
Active: 450mW (typ.)
Standby: 5mW (typ.)
鈥?IDT70V07 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
鈥?M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
鈥?Busy and Interrupt Flags
鈥?On-chip port arbitration logic
鈥?Full on-chip hardware support of semaphore signaling
between ports
鈥?Fully asynchronous operation from either port
鈥?Devices are capable of withstanding greater than 2001V
electrostatic discharge
鈥?LVTTL-compatible, single 3.3V (鹵0.3V) power supply
鈥?Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
DESCRIPTION:
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT70V07 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
FUNCTIONAL BLOCK DIAGRAM
OE
L
OE
R
R/
CE
L
R/
W
L
CE
R
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
15
(1,2)
A
14L
A
0L
MEMORY
ARRAY
Address
Decoder
A
14R
A
0R
15
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
INT
R
SEM
L
(2)
INT
L
M/
S
(2)
2943 drw 01
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE
漏1996 Integrated Device Technology, Inc.
For latest information contact IDT鈥檚 web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2943/3
6.37
1