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用synplify綜合xilinx的IP核，再用ISE implement就出錯了 |
| 作者：boy364 欄目：EDA技術(shù) |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any XILINX primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity FLASH is PORT ( clk : in std_logic; rst : in std_logic; FLASH_out : out std_logic); end FLASH; architecture Behavioral of FLASH is component clock is PORT ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end component; attribute syn_black_box : boolean; attribute syn_black_box of clock: component is true; --attribute syn_black_box of clock: component is true; signal TEMP: std_logic_vector(1 downto 0); signal derive_clk,inter_clk,ready: std_logic; signal inter_signal : std_logic; begin u1: clock PORT map( CLKIN_IN=> clk, RST_IN=> rst, CLK0_OUT=>inter_clk, LOCKED_OUT=>ready, CLKIN_IBUFG_OUT=>open); PROCESS(inter_clk) begin if(ready='1') then if(inter_clk'event and inter_clk='1') then TEMP<=TEMP+1; if(TEMP="11") then derive_clk<= not derive_clk; end if; end if; end if; end PROCESS; PROCESS(derive_clk) begin if(derive_clk'event and derive_clk='1') then inter_signal<=not inter_signal; end if; end PROCESS; FLASH_out<= inter_signal; end Behavioral; 上面是源程序，用了一個(gè)IP核：DCM，用synplify綜合，輸出EDIF文件，用ISE implement，結(jié)果出錯了。提示：ERROR:NgdBuild:604 - logical block 'u1' with type 'clock' could not be resolved. A pin NAME misspelling can cause this, a missing edif or ngc file, or the misspelling of a type NAME. Symbol 'clock' is not supPORTed in target 'spartan3'. 還要在ISE工程中添加什么文件嗎，添加core generator生成的clock.xaw也不行，還是提示同樣的錯誤，高手指點(diǎn)啊，到底怎么回事？ |
| 2樓： | >>參與討論 |
| 作者： boy364 于 2006/6/24 11:52:00 發(fā)布：
知道了 在synplify工程中加入clock.vhd就可以了。犯了個(gè)錯誤 ise implement的時(shí)候并不知道component clock是什么東西 |
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