W39V040FC Data Sheet
512K
脳
8 CMOS FLASH MEMORY
WITH FWH INTERFACE
Table of Contents-
GENERAL DESCRIPTION .............................................................................................................. 3
FEATURES ...................................................................................................................................... 3
PIN CONFIGURATIONS.................................................................................................................. 4
BLOCK DIAGRAM ........................................................................................................................... 5
PIN DESCRIPTION.......................................................................................................................... 6
FUNCTIONAL DESCRIPTION......................................................................................................... 7
6.1
Interface Mode Selection and Description ............................................................................ 7
6.2
Read (Write) Mode ................................................................................................................ 7
6.3
Reset Operation .................................................................................................................... 7
6.4
Accelerated Program Operation............................................................................................ 7
6.5
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP............................... 7
6.6
Sector/Page Erase Command............................................................................................... 8
6.7
Program Operation................................................................................................................ 8
6.8
Hardware Data Protection ..................................................................................................... 8
6.9
Write Operation Status .......................................................................................................... 8
6.10 DQ7: #Data Polling................................................................................................................ 9
6.11 RY/#BY: Ready/#Busy .......................................................................................................... 9
6.12 DQ6: Toggle Bit ..................................................................................................................... 9
6.13 DQ5: Exceeded Timing Limits............................................................................................. 10
6.14 Identification Input pin ID[3:0].............................................................................................. 10
7. REGISTER FOR FWH MODE ....................................................................................................... 11
7.1
General Purpose Inputs Register for FWH Mode ............................................................... 11
7.2
Product Identification Registers........................................................................................... 11
7.3
Block Locking Registers ...................................................................................................... 11
7.4
Register Based Block Locking Value Definitions Table ...................................................... 12
7.5
Read Lock ........................................................................................................................... 12
7.6
Write Lock............................................................................................................................ 12
7.7
Lock Down........................................................................................................................... 12
8. TABLE OF OPERATING MODES ................................................................................................. 13
8.1
Operating Mode Selection - Programmer Mode ................................................................. 13
8.2
Operating Mode Selection - FWH Mode ............................................................................. 13
8.3
FWH Cycle Definition .......................................................................................................... 13
8.4
TABLE OF COMMAND DEFINITION ................................................................................. 14
9. EMBEDDED PROGRAMMING ALGORITHM ............................................................................... 15
10. EMBEDDED ERASE ALGORITHM ............................................................................................... 16
11. EMBEDDED #DATA POLLING ALGORITHM ............................................................................... 17
Publication Release Date: Apr. 11, 2006
Revision A1
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