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W39V040A Datasheet

  • W39V040A

  • NVM > Flash> FWH/LPC Flash Memory

  • Winbond

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W39V040A
512K
脳
8 CMOS FLASH MEMORY
WITH LPC INTERFACE
1. GENERAL DESCRIPTION
The W39V040A is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K
脳
8 bits. For
flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased
in-system with a standard 3.3V power supply. A 12-volt V
PP
is not required. The unique cell architecture
of the W39V040A results in fast program/erase operations with extremely low current consumption. This
device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in
the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs.
But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also
be programmed and erased using standard EPROM programmers.
2. FEATURES
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Single 3.3-volt Operations:
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3.3-volt Read
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3.3-volt Erase
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3.3-volt Program
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Hardware protection:
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Optional 16K byte or 64K byte Top Boot Block
with lockout protection
鈭?/div>
#TBL & #WP support the whole chip hardware
protection
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鈥?/div>
鈥?/div>
Fast Program Operation:
鈭?/div>
Byte-by-Byte programming: 35
碌S
(typ.)
Flexible 4K-page size can be used as Parameter
Blocks
Low power consumption
鈭?/div>
Active current: 12.5 mA (typ. for LPC mode)
Automatic program and erase timing with
internal V
PP
generation
End of program or erase detection
鈭?/div>
Toggle bit
鈭?/div>
Data polling
鈥?/div>
Fast Erase Operation:
鈭?/div>
Chip erase 100 mS (max.)
鈭?/div>
Sector erase 25 mS (max.)
鈭?/div>
Page erase 25 mS (max.)
Fast Read access time: Tkq 11 nS
Endurance: 10K cycles (typ.)
Twenty-year data retention
8 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
Any individual sector or page can be erased
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Latched address and data
TTL compatible I/O
Available packages: 32L PLCC, 32L STSOP
-1-
Publication Release Date: December 19, 2002
Revision A2

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