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STPCE1 Datasheet

  • STPCE1

  • STPC ELITE DATASHEET / X86 CORE GENERAL PURPOSE PC COMPATIBL...

  • 87頁(yè)

  • ETC

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STPC
廬
ELITE
X86 Core General Purpose PC Compatible System - on - Chip
s
s
s
POWERFUL X86 PROCESSOR
64-BIT SDRAM CONTROLLER AT 100MHz
INTEGRATED PCI NORTH / SOUTH
BRIDGE CONTROLLER
ISA MASTER / SLAVE / DMA
16-BIT LOCAL BUS INTERFACE FOR LOW
COST AND EMBEDDED APPLICATIONS
EIDE CONTROLLER
INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
POWER MANAGEMENT UNIT
I虜C INTERFACE
16 ENHANCED GENERAL PURPOSE I/Os.
JTAG IEEE1149.1
PROGRAMMABLE OUTPUT CLOCK UP TO
135MHz
COMMERCIAL AND INDUSTRIAL TEM-
PERATURE RANGES
x86
Core
Host I/F
L.B.
I/F
LOCAL BUS
ST
PC
EL
IT E
s
s
s
s
PBGA388
s
s
s
s
s
Logic Diagram
s
ISA BUS
DESCRIPTION
The STPC Elite integrates a fully static x86
processor up to 133 MHz, fully compatible with
standard x86 processors, and combines it with
powerful chipset to provide a general purpose PC
compatible subsystem on a single device. The
device is packaged in a 388 Ball Grid Array
(PBGA).
The STPC Elite has a low voltage operation with
V
CORE
= 2.5V and has 5V tolerant I/Os (3.3V
output levels).
ISA
I/F
IPC
PCI
I/F
PCI
I/F
EIDE
ctrl
EIDE
PCI
SDRAM
CONTROL
PMU
JTAG
Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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