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STPCE1HDC Datasheet

  • STPCE1HDC

  • Microprocessor

  • 782.88KB

  • 61頁

  • ETC

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STPC
廬
ELITE
X86 Core General Purpose PC Compatible System - on - Chip
s
s
s
s
s
s
s
POWERFUL X86 PROCESSOR
64-BIT SDRAM CONTROLLER
PCI MASTER / SLAVE CONTROLLER
ISA MASTER/SLAVE
16-BIT LOCAL BUS INTERFACE
EIDE CONTROLLER
INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
POWER MANAGEMENT UNIT
I C INTERFACE
16 GENERAL PURPOSE I/O.
JTAG IEEE1149.1
PROGRAMMABLE OUTPUT CLOCK
x86
Core
Host I/F
L.B.
I/F
LOCAL BUS
ST
PC
EL
I TE
PBGA388
s
s
s
s
s
Logic Diagram
DESCRIPTION
The STPC Elite integrates a fully static x86 proc-
essor, fully compatible with standard x86 proces-
sors, and combines it with powerful chipset to pro-
vide a general purpose PC compatible subsystem
on a single device. The device is packaged in a
388 Ball Grid Array (PBGA).
ISA BUS
ISA
I/F
IPC
s
s
s
s
s
s
s
s
X86 Processor core
Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.
Can access up to 4GB of external memory.
8KByte unified instruction and data cache
with write back and write through capability.
Parallel processing integral floating point unit,
with automatic power down.
Clock core speeds up to of 100 MHz in x1
clock mode and 133MHz in x2 mode.
Fully static design for dynamic clock control.
Low power and system management modes.
PCI
EIDE
ctrl
EIDE
PCI
PCI
SDRAM
CONTROL
PMU
JTAG
Issue 0.1 - October 17, 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/61

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