鈩?/div>
LOW THRESHOLD DRIVE
100% AVALANCHE TESTED
LOGIC LEVEL DEVICE
3
1
2
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronis unique "Single Feature Size鈩?quot;
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalanche characteristics and
less critical alignment steps therefore a remark-
able manufacturing reproducibility.
APPLICATIONS
s
HIGH CURRENT, HIGH SWITCHING SPEED
s
MOTOR CONTROL, AUDIO AMPLIFIERS
s
DC-DC & DC-AC CONVERTERS
s
SOLENOID AND RELAY DRIVERS
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
(*)
I
D
I
DM
(鈥?
P
tot
dv/dt
(1)
E
AS (2)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Value
40
40
鹵 16
100
70
400
300
2
3.6
1.4
-65 to 175
175
(1) I
SD
鈮?00A,
di/dt
鈮?40A/碌s,
V
DD
鈮?/div>
32V, T
j
鈮?/div>
T
JMAX
(2) Starting T
j
= 25
o
C, I
AR
= 50A, V
DD
= 30V
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
J
擄C
擄C
(鈥?
Pulse width limited by safe operating area.
(*) Current Limited by package
February 2002
.
1/8
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