ST92F124/ST92F150/ST92F250
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,
E
3 TM
(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
DATA BRIEFING
s
Memories
鈥?Internal Memory: Single Voltage FLASH up to 256
Kbytes, RAM up to 8Kbytes, 1K byte E
3 TM
(Emulat-
ed EEPROM)
鈥?In-Application Programming (IAP)
鈥?224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
TQFP64
14x14
PQFP100
14x20
s
Clock, Reset and Supply Management
鈥?Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
鈥?0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
鈥?PLL Clock Generator (3-5 MHz crystal)
鈥?Minimum instruction time: 80 ns (25 MHz int. clock)
TQFP100
14x14
鈥?One or two full I C multiple Master/Slave Interfaces
supporting Access Bus
鈥?One or two CAN 2.0B (150 version only) Active inter-
faces with:
鈥?Up to 1 MBit/s communication speed
鈥?3 Transmit Mailboxes with priority configuration
by software
鈥?Enhanced Filtering mechanism
鈥?2 prioritized FIFO receive schemes
鈥?Time-Triggered Communication support
DMA controller for reduced processor overhead
10-bit Analog to Digital Converter allowing up to 16
input channels on 100-pin devices or 8 input channels
on 64-pin devices
s
Interrupt Management
鈥?80, 77 or 48 I/O pins (depending on device)
鈥?4 external fast interrupts + 1 NMI
鈥?Up to 16 pins programmable as wake-up or addition-
al external interrupt with multi-level interrupt handler
s
Timers
鈥?16-bit Timer with 8-bit Prescaler, and Watchdog Tim-
er (activated by software or by hardware)
鈥?16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
鈥?Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, 2 Input Captures and two
Output Compares (100-pin devices only)
鈥?Two 16-bit Multifunction Timers, with Prescaler, 2 In-
put Captures and two Output Compares
s
s
s
Instruction Set
鈥?Rich Instruction Set with 14 Addressing Modes
鈥?Division-by-zero trap generation
s
Communication Interfaces
鈥?Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
鈥?One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
鈥?One asynchronous Serial Communications Interface
(on 100-pin versions only)
鈥?J1850 Byte Level Protocol Decoder (JBLPD)
(on F150J versions only)
s
Development Tools
鈥?Versatile Development Tools, including Assembler,
Linker, C-Compiler, Source Level Debugger, Real
Time Operating System (OSEK OS, CMX) and CAN
drivers
鈥?Hardware Emulator, Flash Programming Boards
DEVICE SUMMARY
Features
FLASH - bytes
RAM - bytes
E
3 TM
- bytes
Timers
Serial Interface
ADC
Network Interface
Temp. Range
Packages
ST92F124R9
60K
2K
2 MFT, STIM, WD
SCI, SPI, I C
8 x 10 bits
-
TQFP64
ST92F150C(R/V)1
4K
ST92F150JV1 ST92F150JDV1
128K
6K
1K
ST92F250CV2
256K
8K
2 MFT, 0/2 EFT,
2 MFT, 2 EFT, STIM, WD
STIM, WD
1/2 SCI, SPI, I C
2 SCI, SPI, 2 I C
8/16 x 10 bits
16 x 10 bits
CAN
J1850
2 CAN, J1850
CAN
o
o
o
o
-40 C to 85 C or -40 C to 125 C
P/TQF P100 and TQFP64 PQFP100
P/TQFP100
Rev. 1.1
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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