SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset
September 2000
Revised February 2001
SSTV16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin DDR-I memory modules. The device has
a differential input clock, SSTL-2 compatible data inputs
and a LVCMOS compatible RESET input. The device has
been designed for compliance with the JEDEC DDR mod-
ule and register specifications.
The device is fabricated on an advanced submicron CMOS
process and is designed to operate at power supplies of
less than 3.6V鈥檚.
Features
s
Compliant with DDR-I registered module specifications
s
Operates at 2.5V
鹵
0.2V V
DD
s
SSTL-2 compatible input and output structure
s
Differential SSTL-2 compatible clock inputs
s
Low power mode when device is reset
s
Industry standard 48 pin TSSOP package
Ordering Code:
Order Number
SSTV16857MTD
Package Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Q
1
-Q
14
D
1
-D
14
RESET
CK
CK
V
REF
V
DDQ
V
DD
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Truth Table
RESET
L
H
H
H
H
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
CK
X or
Floating
Q
n
L
L
H
Q
n
Q
n
鈫?/div>
鈫?/div>
L
H
鈫?/div>
鈫?/div>
H
L
L
=
Logic LOW
H
=
Logic HIGH
X
=
Don鈥檛 Care, but not floating unless noted
鈫?=
LOW-to-HIGH Clock Transition
鈫?=
HIGH-to-LOW Clock Transition
漏 2001 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com
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