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SSTV16859 Datasheet

  • SSTV16859

  • Dual Output 13-Bit Register with

  • Fairchild

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SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset
March 2001
Revised July 2002
SSTV16859
Dual Output 13-Bit Register with
SSTL-2 Compatible I/O and Reset
General Description
The SSTV16859 is a dual output 13-bit register designed
for use with 184 and 232 pin DDR-1 memory modules. The
device has a differential input clock, SSTL-2 compatible
data inputs and a LVCMOS compatible RESET input. The
device has been designed to meet the JEDEC DDR mod-
ule register specifications.
The device has been fabricated on an advanced sub-
micron CMOS process and is designed to operate at power
supplies of less than 3.6V鈥檚.
Features
I
Compliant with DDR-I registered module specifications
I
Operates at 2.5V
鹵
0.2V V
DD
I
SSTL-2 compatible input structure
I
SSTL-2 compliant output structure
I
Differential SSTL-2 compatible clock inputs
I
Low power mode when device is reset
I
Industry standard 64 pin TSSOP package
I
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
SSTV16859G
(Note 1)(Note 2)
SSTV16859MTD
(Note 2)
Package Number
BGA96A
MTD64
Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
Ordering code 鈥淕鈥?indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2002 Fairchild Semiconductor Corporation
DS500414
www.fairchildsemi.com

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