PMC-Sierra,Inc.
PM5356
S/UNI-622-MAX
鈥?Counts received section BIP-8 (B1),
line BIP-24 (B2), and path BIP-8 (B3)
errors, and line and path FEBEs.
鈥?Detects LOS, OOF, LOF, LAIS, LRDI,
LOP, PAIS, PRDI and PERDI.
鈥?Provides divide by 8 recovered clock.
鈥?Provides 8 KHz receive frame pulses.
鈥?Performs cell payload scrambling and
descrambling.
鈥?Provides UTOPIA Level 2 and 8-bit
100 MHz UTOPIA Level 3 compliant
system interfaces.
鈥?Provides synchronous 4 cell transmit
and receive FIFO buffers.
622 Mbit/s ATM Physical Layer Device
FEATURES
GENERAL
鈥?ATM OC-12c (622 Mbit/s) PHY
鈥?Provides on-chip clock and data
recovery and clock synthesis.
鈥?Exceeds Bellcore-GR-253 jitter
tolerance and transmit jitter
requirements.
鈥?Provides a generic 8-bit
microprocessor interface for device
control and register access.
鈥?Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
SONET TRANSMITTER
鈥?Provides a transmit frame pulse input
to align the transport frame to a system
reference.
鈥?Provides transmit clock as timing
reference for transmit outputs.
鈥?Inserts register programmable APS
(K1, K2) and synchronization status
(S1) bytes.
鈥?Inserts PAIS, PRDI, LAIS and LRDI.
鈥?Scrambles transmit data stream.
PACKAGING
鈥?Implemented in low power 3.3 Volt
CMOS technology.
鈥?Packaged in a 304 pin ball grid array
(BGA) package.
鈥?Industrial temperature range (-40擄C to
+85擄C).
SONET RECEIVER
鈥?Recovers clock and data.
鈥?Frames to and descrambles recovered
stream.
鈥?Filters and captures Automatic
Protection Switch bytes (K1,K2) and
detects APS byte failure.
鈥?Detects signal degrade and signal
failure threshold crossing alarms.
鈥?Captures and debounces
synchronization status byte (S1).
APPLICATIONS
鈥?Enterprise and Edge ATM switches.
鈥?ATM switches and hubs.
鈥?Multiprotocol switches.
ATM PROCESSOR
鈥?Implements the ATM Forum User
Network Interface Specification.
鈥?Inserts and extracts ATM cells into and
from the SONET SPE.
BLOCK DIAGRAM
SYSSEL
LIFSEL
TRSTB
TFPI
TFPO
TCLK
TDO
TMS
TCK
TDI
TXD+/-
TDREF1,TDREF0
ATP[0]
JTAG Test
Access Port
Tx
Line
I/F
Tx Section
O/H
Processor
Tx Line O/H
Processor
Tx Path O/H
Processor
Tx ATM Cell
Processor
Utopia ATM Level 2
Utopia ATM Level 3
System Interface
TFCLK
TENB
TCA
TSOC
TPRTY
TDAT[15:0]
PTCLK
POUT[7:0]
FPOUT
RBYP
PECLV
REFCLK+/-
RXD+/-
RRCLK+/-
SD
ATP[1]
PICLK
PIN[7:0]
FPIN
OOF
Section
Trace Buffer
Path Trace
Buffer
Rx
Line
I/F
Rx Section
O/H
Processor
Rx Line O/H
Processor
Rx Path O/H
Processor
Rx ATM Cell
Processor
RFCLK
RENB
RCA
RSOC
RPRTY
RVAL
RDAT[15:0]
Rx APS, Sync
Status, BERM
Microprocessor
Interfaces
RALARM
RFPO
RCLK
APSP[4:0]
D[7:0]
A[8:0]
CSB
RDB
PMC-1981279 (R3)
RSTB
WRB
INTB
ALE
漏 2001 PMC-Sierra, Inc.
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