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NTE6850 Datasheet

  • NTE6850

  • Integrated Circuit NMOS, Asynchronous Communications Interfa...

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NTE6850
Integrated Circuit
NMOS, Asynchronous Communications
Interface Adapter
Description:
The NTE6850 Asynchronous Communications Interface Adapter provides the data formatting and
control to interface serial asynchronous data communications information to bus organized systems
such as the NTE6800 Microprocessing Unit.
The bus interface of the NTE6850 includes select, enable, read/write, interrupt and bus interface logic
to allow data transfer over an 8鈥揵it bidirectional data bus. The parallel data of the bus system is serial-
ly transmitted and received by the asynchronous data interface, with proper formatting and error
checking. The functional configuration of the ACIA is programmed via the data bus during system
initialization. A programmable control register provides variable word lengths, clock division ratios,
transmit control, receive control, and interrupt control. For peripheral or modem operation, three con-
trol lines are provided. These lines allow the ACIA to interface directly with the NTE6860 0鈥?00 bps
digital modem.
Features:
D
8鈥揃it and 9鈥揃it Transmission
D
Optional Even and Odd Parity
D
Parity, Overrun and Framing Error Checking
D
Programmable Control Register
D
Optional
梅1, 梅16,
and
梅64
Clock Modes
D
Up to 1.0 Mbps Transmission
D
False Start Bit Deletion
D
Peripheral/Modem Control Functions
D
Double Buffered
D
One鈥揝top or Two鈥揝top Bit Operation
Absolute Maximum Ratings:
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?.3 to +7.0V
Input Voltage, V
in
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?.3 to +7.0V
Operating Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0擄 to 70擄C
Storage Temperature Range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?5擄 to +150擄C
Thermal Resistance, Junction鈥搕o鈥揂mbient, R
thJA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120擄C/W
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.
either V
SS
or V
CC
).

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