鈥?/div>
Expandable to 16-bits or more with serial input
DESCRIPTION
The 74F835 is a high speed 8-bit parallel/serial-in, serial-out shift
register whose parallel inputs have been connected to an internal
octal two-to-one multiplexer with all the 鈥淏鈥?inputs connected to an
octal latch.
This 24-pin part is specifically designed for video bit shifting, where
interleaved loading is desired and parts count is critical. It is useful in
any design where a 2:1 mux input with a transparent latch is
needed.
TYPICAL
SUPPLY CURRENT
(TOTAL)
45mA
one package
PIN CONFIGURATION
PE 1
CP
D4A
D4B
D5A
D5B
D6A
D6B
D7A
2
3
4
5
6
7
8
9
24 V
CC
23 D3B
22 D3A
21 D2B
20 D2A
19 D1B
18 D1A
17 D0B
16 D0A
15 DS
14 SA/B
13 LE
D7B 10
Q7 11
GND 12
SF01355
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
鹵10%,
T
amb
= 0擄C to +70擄C
N74F835N
N74F835D
PACKAGE
DRAWING
NUMBER
SOT222-1
SOT137-1
TYPE
74F835
TYPICAL f
MAX
150MHz
24-pin plastic
Slim DIP (300 mil)
24-pin plastic SOL
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0A 鈥?D7A
D0B 鈥?D7B
DS
CP
SA/B
LE
PE
Q7
DESCRIPTION
Parallel data inputs
Latched Parallel data inputs
Serial data input
Shift Register Clock input (active rising edge)
Mux Select
Latch Enable input (for B inputs)
Parallel Enable input
Output
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE HIGH/LOW
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20碌A(chǔ) in the High state and 0.6mA in the Low state.
1990 Jan 08
1
853鈥?615 99490