鈥?/div>
Direct Overriding Clear
DESCRIPTION
The 74F322 is an 8-bit shift register with provision for either serial or
parallel loading and with 3-State parallel outputs plus a bi-state
serial output. Parallel data inputs and outputs are multiplexed to
minimize pin count. State changes are initiated by the rising edge of
the clock. Four synchronous modes of operation are possible: hold
(store), shift right with serial entry, shift right with sign extend, and
parallel load. An asynchronous Master Reset (MR) input overrides
clocked operation and clears the registers.
The 74F322 contains eight D-type edge triggered flip-flops and the
interstage gating required to perform right shift and the intrastage
gating necessary for hold and synchronous parallel load operations.
A Low signal on RE enables shifting or parallel loading, while a High
signal enables the hold mode. A High signal on S/P enables shift
right, while a Low signal disables the 3-State output buffers and
enables parallel loading. In the shift right mode a High signal on SE
enables serial entry from either D0 or D1, as determined by the S
input. A Low signal on SE enables shift right, but Q7 reloads its
contents, thus performing the sign extend function. A High signal on
OE disables the 3-State output buffers, regardless of the other
control inputs. In this condition the shifting and loading operations
can still be performed.
PIN CONFIGURATION
RE
S/P
D0
I/O0
I/O2
I/O4
I/O6
OE
MR
1
2
3
4
5
6
7
8
9
20 V
CC
19 S
18 SE
17 D1
16 I/O1
15 I/O3
14 I/O5
13 I/O7
12 Q7
11 CP
GND 10
SF00874
TYPE
74F322
TYPICAL f
MAX
125MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
60mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
鹵10%,
T
amb
= 0擄C to +70擄C
N74F322N
N74F322D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0, D1
S
SE
CP
S/P
RE
MR
OE
Q7
I/On
Serial data inputs
Serial data select input
Sign Extend input
Clock Pulse input (Active rising edge)
Serial (High) or Parallel (Low) mode control input
Register Enable input (Active Low)
Asynchronous Master Reset input (Active Low)
Output Enable input (Active Low)
Bi-state serial output
Multiplexed parallel data inputs or
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
3.5/1.0
150/40
LOAD VALUE
HIGH/LOW
20碌A(chǔ)/0.6mA
20碌A(chǔ)/1.2mA
20碌A(chǔ)/1.8mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
1.0mA/20mA
70碌A(chǔ)/0.6mA
3.0mA/24mA
3-State parallel outputs
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20碌A(chǔ) in the High State and 0.6mA in the Low state.
1988 Apr 22
1
853-0366 93020
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