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MT8941B Datasheet

  • MT8941B

  • CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL

  • 133.82KB

  • 22頁

  • MITEL

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CMOS ST-BUS鈩?FAMILY
MT8941B
Advanced T1/CEPT Digital Trunk PLL
Features
鈥?/div>
鈥?/div>
Provides T1 clock at 1.544 MHz locked to an 8
kHz reference clock (frame pulse)
Provides CEPT clock at 2.048 MHz and ST-BUS
clock and timing signals locked to an internal or
external 8 kHz reference clock
Typical inherent output jitter (un鏗乴tered)= 0.07
UI peak-to-peak
Typical jitter attenuation at: 10 Hz=23 dB,100
Hz=43 dB, 5 to 40 kHz
鈮?/div>
64 dB
Jitter-free 鈥淔REE-RUN鈥?mode
Uncommitted two-input NAND gate
Low power CMOS technology
DS5186
ISSUE 1
June 1999
Ordering Information
MT8941BE
MT8941BP
24 Pin Plastic DIP (600 mil)
28 Pin PLCC
-40擄C to +85擄C
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Description
The MT8941B is a dual digital phase-locked loop
providing the timing and synchronization signals for
the T1 or CEPT transmission links and the ST-BUS.
The 鏗乺st PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.
The MT8941B offers improved jitter performance
over the MT8940. The two devices also have some
functional differences, which are listed in the section
on 鈥淒ifferences between MT8941B and MT8940鈥?
Applications
鈥?/div>
鈥?/div>
Synchronization and timing control for T1
and CEPT digital trunk transmission links
ST- BUS clock and frame pulse source
F0i
DPLL #1
C12i
2:1 MUX
CVb
Variable
Clock
Control
CV
ENCV
MS0
MS1
MS2
MS3
C8Kb
Mode
Selection
Logic
Frame Pulse
Control
Input
Selector
4.096 MHz
Clock
Control
DPLL #2
Clock
Generator
Ai
Bi
2.048 MHz
Clock
Control
F0b
C4b
C4o
ENC4o
C16i
C2o
C2o
ENC2o
Yo
V
DD
V
SS
RST
Figure 1 - Functional Block Diagram
1

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