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MT8986 Datasheet

  • MT8986

  • CMOS ST-BUS? FAMILY

  • Zarlink   Zarlink

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CMOS ST-BUS
TM
Family
MT8986
Multiple Rate Digital Switch
Data Sheet
Features
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256 x 256 or 512 x 256 switching configurations
8-bit or 4-bit channel switching capability
Guarantees frame integrity for wideband
channels
Automatic identification of ST-BUS/GCI interfaces
Accepts serial streams with data rates up to
8.192 Mb/s
Rate conversion from 2.048 Mb/s to 4.096 or
8.192 Mb/s and vice-versa
Programmable frame offset on inputs
Per-channel three-state control
Per-channel message mode
Control interface compatible to Intel/Motorola
CPUs
Low power consumption
Ordering Information
MT8986AE
MT8986AP
MT8986AL
MT8986APR
MT8986AP1
MT8986APR1
40 Pin PDIP
44 Pin PLCC
44 Pin MQFP
44 Pin PLCC
44 Pin PLCC*
44 Pin PLCC*
*Pb Free Matte Tin
February 2005
Tubes
Tubes
Trays
Tape & Reel
Tubes
Tape & Reel
-40擄C to +85擄C
Description
The Multiple Rate Digital Switch (MRDX) is an
upgraded version of Zarlink's MT8980D Digital Switch
(DX). It is pin compatible with the MT8980D and
retains all of its functionality. This device is designed to
provide simultaneous connections (non-blocking) for
up to 256 64 kb/s channels or blocking connections for
up to 512 64 kb/s channels. The serial inputs and
outputs connected to MT8986 may have 32 to 128
64 kb/s channels per frame with data rates ranging
from 2048 up to 8192 kb/s. The MT8986 provides per-
channel selection between variable and constant
throughput delays allowing voice and grouped data
channels to be switched without corrupting the data
sequence integrity.
In addition, the MT8986 can be used for switching of
32 kb/s channels in ADPCM applications. The MT8986
is ideal for medium size mixed voice and data
switching/processing applications.
V
DD
V
SS
ODE
Applications
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Medium size digital switch matrices
Hyperchannel switching (e.g., ISDN H0)
MVIP
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interface functions
Serial bus control and monitoring
Centralized voice processing systems
Voice/Data multiplexer
32 kbit/s channel switching
*
*
*
*
*
*
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Serial
to
Parallel
Converter
Timing
Unit
Multiple Buffer Data
Memory
Output
MUX
Parallel
to
Serial
Converter
Connection
Memory
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8 *
STo9 *
Internal Registers
Microprocessor
Interface
* 44 Pin only
CLK FR AS/ IM
ALE *
DS CS
RD
R/W A0/ DTA AD7/
AD0
WR A7
CSTo
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.

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