鈥?/div>
-40擄C to +85擄C
Description
The MT8941B is a dual digital phase-locked loop
providing the timing and synchronization signals for the
T1 or CEPT transmission links and the ST-BUS. The
first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.
The MT8941B offers improved jitter performance over
the MT8940. The two devices also have some
functional differences, which are listed in the section on
鈥淒ifferences between MT8941B and MT8940鈥?
Applications
鈥?/div>
鈥?/div>
Synchronization and timing control for T1
and CEPT digital trunk transmission links
ST- BUS clock and frame pulse source
F0i
DPLL #1
C12i
2:1 MUX
Variable
Clock
Control
CVb
CV
ENCV
MS0
MS1
MS2
MS3
C8Kb
Mode
Selection
Logic
Frame Pulse
Control
Input
Selector
4.096 MHz
Clock
Control
DPLL #2
F0b
C4b
C4o
ENC4o
C2o
C2o
ENC2o
C16i
Clock
Generator
Ai
Bi
2.048 MHz
Clock
Control
Yo
V
DD
V
SS
RST
Figure 1 - Functional Block Diagram
1
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Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
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