Multiple devices available with different bank sizes (Refer to 鈥淢BM29DL16XTD/BD Device Bank Divisions Table鈥?/div>
in
sGENERAL
DESCRIPTION)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
鈥?Single 3.0 V read, program, and erase
Minimizes system level power requirements
(Continued)
s
PRODUCT LINE UP
Part No.
Ordering Part No.
V
CC
= 3.3 V
鈥?.3 V
+0.3 V
+0.6 V
MBM29DL16XTD/MBM29DL16XBD
70
鈥?/div>
70
70
30
鈥?/div>
90
90
90
35
V
CC
= 3.0 V
鈥?.3 V
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
s
PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
48-ball plastic FBGA
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-48P-M13)
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