FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20841-4E
FLASH MEMORY
CMOS
8M (1M
脳
8/512K
脳
16) BIT
MBM29F800TA
-55/-70/-90
/MBM29F800BA
-55/-70/-90
s
FEATURES
鈥?Single 5.0 V read, write, and erase
Minimizes system level power requirements
鈥?Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
鈥?Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN 鈥?Normal Bend Type, PFTR 鈥?Reversed Bend Type)
44-pin SOP (Package suffix: PF)
鈥?Minimum 100,000 write/erase cycles
鈥?High performance
55 ns maximum access time
鈥?Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
鈥?Boot Code Sector Architecture
T = Top sector
B = Bottom sector
鈥?Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
鈥?Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
鈥?Data Polling and Toggle Bit feature for detection of program or erase cycle completion
鈥?Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
鈥?Low Vcc write inhibit
鈮?/div>
3.2 V
鈥?Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
鈥?Hardware RESET pin
Resets internal state machine to the read mode
鈥?Sector protection
Hardware method disables any combination of sectors from write or erase operations
鈥?Temporary sector unprotection
Temporary sector unprotection via the RESET pin.
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
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