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ISPPAC80-01PI Datasheet

  • ISPPAC80-01PI

  • In-System Programmable Analog Circuit

  • 342.43KB

  • 19頁(yè)

  • LATTICE   LATTICE

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ispPAC 80
TM
In-System Programmable Analog Circuit
Features
鈥?IN-SYSTEM PROGRAMMABLE (ISP鈩? ANALOG
鈥?Instrument Amplifier Gain Stage
鈥?Precision Active Filtering (50kHz to 500kHz)
鈥?Continuous-Time Fifth Order Low Pass Topology
鈥?Dual, A/B Configuration Memory
鈥?Non-Volatile E
2
CMOS Cells
鈥?IEEE 1149.1 JTAG Serial Port Programming
鈥?UNIQUE FLEXIBILITY AND PERFORMANCE
鈥?Programmable Gain Range (0dB to 20dB)
鈥?Implements Multiple Filter Types: Elliptical,
Chebyshev, Bessel, Butterworth, Linear Phase,
Gaussian and Legendre
鈥?Low Distortion (THD < -74dB max @ 100kHz)
鈥?Auto-Calibrated Input Offset Voltage
鈥?TRUE DIFFERENTIAL I/O
鈥?High CMR (58dB) Instrument Amplifier Input
鈥?2.5V Common Mode Reference on Chip
鈥?Rail-to-Rail Voltage Outputs
鈥?SINGLE SUPPLY 5V OPERATION
鈥?Power Dissipation of 165mW
鈥?16-Pin Plastic SOIC, PDIP Packages
鈥?APPLICATIONS INCLUDE INTEGRATED
鈥?Single +5V Supply Signal Conditioning
鈥?Programmable Filters With Fully Differential I/O
鈥?Analog Front Ends, 12-Bit Data Acq. Systems
鈥?DSP System Front End Signal Conditioning
鈥?High-Performance Reconstruction Filters
Functional Block Diagram
TMS
TCK
TDI
TDO
CS
CAL
ENSPI
GND
1
2
IA
OA
16 VS
15 TEST
14 OUT+
5th Order LPF
E2CMOS Cfg A
Ref & Auto-Cal
E2CMOS Cfg B
ISP Control
3
4
5
6
7
8
13 OUT鈥?/div>
12 TEST
11 IN+
10 IN鈥?/div>
9 VREFOUT
ispPAC80
Description
The ispPAC80 is a member of the Lattice family of In-System
Programmable analog circuits, digitally configured via non-
volatile E
2
CMOS
廬
technology.
Analog building blocks, called PACell鈩?s), replace traditional
analog components such as opamps, eliminating the need for
external resistors and capacitors. With no requirement for
external configuration components, ispPAC80 expedites the
design process, simplifying prototype circuit implementation
and change, while providing high-performance integrated func-
tionality. With all components on chip, there is no longer a
concern of performance degradation due to component mis-
match or other external factors. The ispPAC80 provides reliable
and repeatable performance, every time.
Designers configure the ispPAC80 and verify its performance
using PAC-Designer鈩? an easy to use, Microsoft Windows
廬
compatible program. A filter configuration database is provided
whereby thousands of different configurations can be realized.
No special understanding of filter synthesis is required beyond
that of general specifications such as corner frequency and
stopband attenuation, etc. The software lists the possible
choices that meet the designer鈥檚 specifications which can then
be loaded directly into either of two device
(A/B) configurations from the lookup table. Device program-
ming is supported using PC parallel port I/O operations.
The ispPAC80 is configured through its IEEE Standard 1149.1
compliant serial port. The flexible In-System Programming
capability enables programming, verification and reconfig-
uration, if desired, directly on the printed circuit board.
Typical Application Diagram
5V
ispPAC80
5V
12-Bit Differential
Input ADC
Ain+
Ain-
A/B & Gain
SPI Control
VREFout
Reference
Vin
5V
DSP
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com
March 2000
pac80_03
1

ISPPAC80-01PI 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡(jiǎn)單可編程邏輯器件

  • ISPPA

  • 7 ns

  • 3 V to 3.6 V

  • + 85 C

  • - 40 C

  • PDIP-16

  • Through Hole

  • 20

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