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ispPAC20 Datasheet

  • ispPAC20

  • User Programmable Special Function ASIC

  • Lattice   Lattice

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ispPAC 20
In-System Programmable Analog Circuit
Features
鈥?IN-SYSTEM PROGRAMMABLE (ISP鈩? ANALOG
鈥?Two Instrument Amplifier Gain/Attenuation Stages
鈥?Signal Summation (Up to 3 Inputs)
鈥?Precision Active Filtering (10kHz to 100kHz)
鈥?8-Bit DAC and Fast Dual Comparator
鈥?Non-Volatile E
2
CMOS
廬
Cells (10,000 Cycles)
鈥?IEEE 1149.1 JTAG Serial Port Programming
鈥?LINEAR ELEMENT BUILDING BLOCKS
鈥?Programmable Gain Range (0dB to 40dB)
鈥?Bandwidth of 550kHz (G=1), 330kHz (G=10)
鈥?Low Distortion (THD < -74dB max @ 10kHz)
鈥?Auto-Calibrated Input Offset Voltage
鈥?TRUE DIFFERENTIAL I/O
鈥?High CMR (69dB) Instrument Amplifier Inputs
鈥?2.5V Common Mode Reference on Chip
鈥?Rail-to-Rail Voltage Outputs
鈥?Single Supply 5V Operation
鈥?44-PIN PLASTIC PLCC AND TQFP PACKAGES
鈥?APPLICATIONS INCLUDE INTEGRATED:
鈥?Single +5V Supply Signal Conditioning
鈥?Active Filters, Gain Stages, Summing Blocks
鈥?Analog Front Ends, 12-Bit Data Acq. Systems
鈥?Precision Voltage Controlled Oscillator
鈥?Synchronous Detection Circuits
鈥?Precision Rectification & Other Non-Linear Functions
廬
Functional Block Diagram
VCC
MSEL
GND
OUT1
OUT2
IN1
IA
IA
OA
CP
Logic
CP1OUT
Logic
Window
IN2
CP
IA
IN3
IA
OA
3VREF
1.5VREF
CP2OUT
Analog Routing Pool
CPIN
E
2
CMOS Mem
Auto-Cal
Reference
ISP Control
DAC
DACOUT
Description
The ispPAC20 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E
2
CMOS technology.
Analog building blocks, called PACblocks, replace tradi-
tional analog components such as opamps and active
filters, eliminating the need for most external resistors and
capacitors. Also included are an 8-bit DAC and dual com-
parators. With no requirement for external configuration
components, ispPAC20 expedites the design process,
simplifying prototype circuit implementation and change,
while providing high-performance integrated functionality.
Designers configure the ispPAC20 and verify its perfor-
mance using PAC-Designer
廬
, an easy-to-use, Microsoft
Windows
廬
compatible program. Device programming is
supported using PC parallel port I/O operations.
The ispPAC20 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-System
Programming capability enables programming, verification
and reconfiguration if desired, directly on the printed circuit
board.
Typical Application Diagram
5V
Vin
5V
12-Bit
Differential
Input ADC
Copyright 漏 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
PC
VREFOUT
ENSPI
D0...D7
DMODE
CAL
JTAG/SPI
ispPAC20
CS
CMVIN
Ain+
Ain-
Ref+
DAC
Ref-
May 2001
pac20_05
1

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