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ISPCLOCK5600 Datasheet

  • ISPCLOCK5600

  • In-System Programmable, Zero-Delay Clock Generator with Univ...

  • 47頁(yè)

  • LATTICE   LATTICE

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ispClock 5600 Family
鈩?/div>
In-System Programmable, Zero-Delay Clock Generator
with Universal Fan-Out Buffer
November 2004
Preliminary Data Sheet
Features
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
10MHz to 320MHz Input/Output Operation
Low Output to Output Skew (<50ps)
Low Jitter Peak-to-Peak (<60ps)
Up to 20 Programmable Fan-out Buffers
鈥?Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
鈥?Programmable output impedance
- 40 to 70鈩?in 5鈩?increments
鈥?Programmable slew rate
鈥?Up to 10 banks with individual V
CCO
and GND
- 1.5V, 1.8V, 2.5V, 3.3V
鈥?Programmable lock detect
鈥?Multiply and divide ratio controlled by
- Input divider (5 bits)
- Feedback divider (5 bits)
- Five output dividers (5 bits)
鈥?Programmable On-chip Loop Filter
鈥?Up to +/- 12ns skew range
鈥?Coarse and
鏗乶e
adjustment modes
鈻?/div>
Up to Five Clock Frequency Domains
鈻?/div>
Flexible Clock Reference and External
Feedback Inputs
鈥?Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
鈥?Clock A/B selection multiplexer
鈥?Feedback A/B selection multiplexer
鈥?Programmable termination
鈻?/div>
Four User-programmable Pro鏗乴es Stored in
E
2
CMOS
廬
Memory
鈥?Supports both test and multiple operating
con鏗乬urations
鈻?/div>
Fully Integrated High-Performance PLL
鈻?/div>
Precision Programmable Phase Adjustment
(Skew) Per Output
鈥?16 settings; minimum step size 195ps
- Locked to VCO frequency
鈻?/div>
Full JTAG Boundary Scan Test In-System
Programming Support
鈻?/div>
Exceptional Power Supply Noise Immunity
鈻?/div>
Commercial (0 to 70擄C) and Industrial
(-40 to 85擄C) Temperature Ranges
鈻?/div>
100-pin and 48-pin TQFP Packages
鈻?/div>
Applications
鈥?Circuit board common clock generation and
distribution
鈥?PLL-based frequency generation
鈥?High fan-out clock buffer
鈥?Zero-delay clock buffer
Product Family Block Diagram
LOCK DETECT
OUTPUT
DIVIDERS
BYPASS
MUX
*
V0
V1
V2
V3
V4
PLL CORE
Internal/External
Feedback
Select
*
OUTPUT
ROUTING
MATRIX
CLOCK OUTPUTS
SKEW
CONTROL
OUTPUT
DRIVERS
REFERENCE
INPUTS
M
PHASE/
FREQUENCY
DETECTOR
FILTER
VCO
N
FEEDBACK
INPUTS
JTAG
INTERFACE
&
E
2
CMOS
MEMORY
Multiple Profile
Management Logic
0
1
2
3
INTERNAL FEEDBACK PATH
* Input Available only on ispClock5620
漏 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci鏗乧ations and information herein are subject to change without notice.
www.latticesemi.com
1
clk5600_01

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