鈥?/div>
t
pd
= 7.5 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Eraseable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?IN-SYSTEM PROGRAMMABLE
鈥?In-System Programmable (ISP鈩? 5V Only
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Enhanced Pin Locking Capability
鈥?Four Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control to
Minimize Switching Noise
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispLSI DEVELOPMENT TOOLS
ispVHDL鈩?Systems
鈥?VHDL/Verilog-HDL/Schematic Design Options
鈥?Functional/Timing/VHDL Simulation Options
ispDS+鈩?VHDL Synthesis-Optimized Logic Fitter
鈥?Supports Leading Third-Party Design Environments
for Schematic Capture, Synthesis and Timing
Simulation
鈥?Static Timing Analyzer
ispDS鈩?Software
鈥?Lattice HDL or Boolean Logic Entry
鈥?Functional Simulator and Waveform Viewer
ISP Daisy Chain Download Software
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
A0
Output Routing Pool
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
D7
D5
Output Routing Pool
0139G1A-isp
D Q
A1
A2
A3
A4
A5
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
D6
Logic
D Q
Global Routing Pool (GRP)
Array
D Q
GLB
D4
D3
D2
D1
D0
D Q
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
CLK
Description
The ispLSI 1048E is a High-Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E fea-
tures 5V in-system programmability and in-system
diagnostic capabilities. The ispLSI 1048E offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. A
functional superset of the ispLSI 1048 architecture, the
ispLSI 1048E device adds two new global output enable
pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1鈥7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright 漏 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
July 1998
1048E_08
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