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INTEGRA Datasheet

  • INTEGRA

  • Integra L64754 ISDB-S DVB/DSS Satellite Receiver

  • 2頁

  • ETC

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Integra L64754 ISDB-S
DVB/DSS Satellite Receiver
TM
OVERVIEW
The L64754 is a satellite receiver demodulator designed specifically to
meet the needs of Japanese satellite broadcast digital TV. Providing maximum
integration and flexibility for system designers at a minimum cost, the L64754
chip reduces the number of external components required to build a system.
LSI Logic fabricates the L64754 using its G12, 1.8 core/3.3 volt I/O, 0. I 8-
micron, HCMOS process technology.
The L64754 demodulator interfaces with any tuner IC, which directly down-
converts satellite signal from L-band to baseband, and includes an on-chip synthesizer
controller. The L64754 generates control signals for a tuner IC synthesizer (using
frequency information programmed into the L64754 configuration registers), and
generates dual AGC control voltages for the two-stage automatic gain control on a
tuner IC chip.
The L64754 satellite demodulator contains two main blocks: a
BPSK/QPSK/8PSK demodulator and a concatenated FEC decoder.
The B/Q/8PSK demodulator performs demodulation for any of the three
modulation formats, a method of extracting a digital signal from a phase-modulated
analog signal. The B/Q/8PSK module is designed specifically for a satellite
broadcast digital TV receiver, and is compliant with the Japanese ISDB-S standard.
The demodulator works as per the European digital video broadcast (DVB-S)
standard and the technical specifications for DSS systems.
FEATURES
鈥?/div>
On-chip dual differential 6-bit
A/D converters
鈥?/div>
Variable data rate of 1 to 45
Mbaud
鈥?/div>
Serial host interface compatible
with the LSI Logic serial control
bus interface
鈥?/div>
Correction for Quadrature
phase, amplitude imbalance
鈥?/div>
Integrated PLL for clock synthesis
for use of fundamental mode
crystal
鈥?/div>
Fast channel-switching mode
鈥?/div>
Anti-aliasing filters
鈥?/div>
On-chip digital clock
synchronization
鈥?/div>
Programmable matched filter
鈥?/div>
Synthesizer control-programmable
counters
鈥?/div>
Power estimation for AGC
control-dual AGC outputs to
allow two-stage AGC
鈥?/div>
On-chip C/N, BER estimators
To Tuner IC?
AGC
Control
Carrier
Loop Control
B/Q/8PSK
Demodulator
鈥?/div>
Bit-error monitoring for channel
Channel Imput
From Tuner IC
N/T "
I
Q
Clk (from L64754
onchip PLL)
To Tuner IC
To Tuner IC
Synthesizer
Control
Lowpass Filter
Control
Dual
ADC
Interpolator /Decimation Filter
Timimg
Loop Control
Matched
Filter
Output
Control
DEMI
1/T
DEMQ
Linear
Eq.
performance measurements for
all possible ISDB-S/DVB/DSS
rates
鈥?/div>
On-chip block de-interleaver
鈥?/div>
Power-down and Standby
Microcontroller Data and Address Bus
External Microcontroller Data and Address Bus
modes
鈥?/div>
On-chip controller frees host
Microcontroller Data and Address Bus
Block
Deinterleaver
and Frame Data
Descrambler
processor
TMCC
Descrambler
Pragmatic
TCM Decoder
Channel
Output
(MPEG-2)
Transport
Stream)
Out, Interface
Reed Solomon
Decoder
FEC Decoder
Pipeline
TMCC Control
The
Communications
Company
TM
Integra鈩?L64754 Block Diagram

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