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IDT85304 Datasheet

  • IDT85304

  • LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER

  • 11頁(yè)

  • IDT

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IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V
LVPECL FANOUT BUFFER
FEATURES:
鈥?Five differential 3.3V LVPECL outputs
鈥?Selectable differential CLK, xCLK, or LVPECL clock inputs
鈥?CLK, xCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, SSTL, and HCSL
鈥?PCLK, xPCLK supports the following input types: LVPECL, CML,
and SSTL
鈥?Maximum output frequency: 650MHz
鈥?Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on xCLK input
鈥?Output skew: 35ps (max.)
鈥?Part-to-part skew: as low as 150ps
鈥?Propagation delay: 2.1ns (max.)
鈥?3.3V operating supply
鈥?Available in TSSOP package
IDT85304-01
DESCRIPTION:
The IDT85304-01 is a low skew, high performance 1-to-5 differential-to-
3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The
CLK/ xCLK pair can accept most standard differential input levels. The PCLK/
xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable
is internally synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the IDT85304-
01 ideal for those applications that demand well-defined performance and
repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
D
Q
CLK
xCLK
PCLK
xPCLK
1
0
LE
Q0
xQ0
Q1
xQ1
Q2
CLK_SEL
xQ2
Q3
xQ3
Q4
xQ4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2004
Integrated Device Technology, Inc.
MAY 2004
DSC 6174/2

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