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4 channel CODEC with on-chip digital filters
Selectable A-law or
碌-law
companding
Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
- Internal timing automatically adjusted based on MCLK and
frame sync signal
Separate PCM and master clocks
Single PCM port with up to 8.192 MHz data rate (128 time slots)
Transhybrid balance impedance hardware adjustable via external
components
Transmit gains hardware adjustable via external components
Low power +5.0 V CMOS technology
+5.0 V single power supply
Package available: 32 pin PLCC, 44 pin TQFP
FUNCTIONAL BLOCK DIAGRAM
IIN1
VOUT1
IIN2
VOUT2
IIN3
VOUT3
Anolog Front End
CH1
PCM TSA 1
PCM TSA 2
PCM TSA 3
PCM TSA 4
FSX1
FSR1
FSX2
FSR2
FSX3
FSR3
FSX4
FSR4
DX
TSC
DR
PCLK
Anolog Front End
CH2
DSP
Anolog Front End
CH3
IIN4
VOUT4
Anolog Front End
CH4
PCM Interface
MCLK
IREF
CNF
Clock
&
Reference Circuits
PDN 1~ 4
Control
A/碌
AGND
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
1
漏2003
Integrated Device Technology, Inc.
DGND
VCCA
VCCD
APRIL 3, 2003
DSC-6034/4