256K x 32
CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7MP4045
IDT7MP4145
FEATURES:
鈥?High density 1 megabyte static RAM module
(IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120)
鈥?Low profile 64 pin ZIP (Zig-zag In-line vertical Package)
or 64 pin SIMM (Single In-line Memory Module) for
IDT7MP4045 and 72 pin SIMM (Single In-line Memory
Module) for IDT7MP4145
鈥?Very fast access time: 15ns (max.)
鈥?Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
鈥?Single 5V (鹵10%) power supply
鈥?Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
鈥?Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7MP4045/4145 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability of
four chip select lines (one for each group of two RAMs)
provides byte access. The IDT7MP4045 is available with
access time as fast as 10ns with minimal power consumption.
The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zig-
zag In-line vertical Package)or a 64 pin SIMM (Single In-line
Memory Module) where as the 7MP4145 is packaged in a 72
pin SIMM (Single In-line Memory Module). The 4045 ZIP
configuration allows 64 pins to be placed on a package 3.65
inches long and 0.365 inches wide. The 7MP4045 ZIP is only
0.585 inches high, this low profile package is ideal for systems
with minimum board spacing while the SIMM configuration
allows use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4045/4145 are TTL-
compatible and operate from a single 5V supply. Full asyn-
chronous circuitry requires no clocks or refresh for operation
and provides equal access and cycle times for ease of use.
Identification pins are provided for applications in which
different density versions of the module are used. In this way,
the target system can read the respective levels of PD
pins
to
determine a 256K depth.
The contact pins are plated with 100 micro-inches of nickel
covered by 30 micro-inches minimum of selective gold.
PIN CONFIGURATION 鈥?7MP4045
(1)
1
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
ZIP,
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
WE
CS
1
CS
3
A
14
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
PD
0
鈥?GND
PD
1
鈥?GND
FUNCTIONAL BLOCK DIAGRAM
CS
1
CS
2
CS
3
CS
4
ADDRESS
18
2
SIMM
TOP VIEW
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
CS
2
CS
4
A
17
PD
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
OE
WE
OE
8
256K x 32
RAM
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
2703 drw 01
8
8
8
2703 drw 02
I/O
0-31
PIN NAMES
I/O
0
鈥?/div>
31
A
0
鈥?/div>
17
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
Ground
No Connect
2703 tbl 01
CS
1鈥?
WE
OE
PD
0鈥?
V
CC
GND
NC
NOTE:
1. Pins 2 and 3 (PD
0
and PD
1
) are read by the user to determine the density
of the module. If PD
0
reads GND and PD
1
reads GND, then the module
has a 256K depth.
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
漏1996
Integrated Device Technology, Inc.
SEPTEMBER 1996
DSC-2703/7
15.2
1
1
2
3
4
5
6
7
8
