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IDT79R3500 Datasheet

  • IDT79R3500

  • RISC CPU PROCESSOR RISCore⑩

  • 145.56KB

  • 16頁

  • IDT

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IDT79R3500 RISC CPU PROCESSOR RISCore
廬
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RISC CPU PROCESSOR
RISCore
鈩?/div>
IDT79R3500
Integrated Device Technology, Inc.
FEATURES:
鈥?Efficient Pipelining鈥擳he CPU鈥檚 5-stage pipeline design
assists in obtaining an execution rate approaching one
instruction per cycle. Pipeline stalls and exceptions are
handled precisely and efficiently.
鈥?On-Chip Cache Control鈥擳he IDT79R3500 provides a
high-bandwidth memory interface that handles separate
external Instruction and Data Caches ranging in size from
4 to 256kBs each. Both caches are accessed during a
single CPU cycle. All cache control is on-chip.
鈥?On-Chip Memory Management Unit鈥擜 fully-associative,
64-entry Translation Lookaside Buffer (TLB) provides fast
address translation for virtual-to-physical memory map-
ping of the 4GB virtual address space.
鈥?Dynamically able to switch between Big- and Little- Endian
byte ordering conventions.
鈥?Optimizing Compilers are available for C, FORTRAN,
Pascal, COBOL, Ada, PL/1 and C++.
鈥?20 through 40MHz clock rates yield up to 32VUPS sus-
tained throughput.
鈥?Supports independent multi-word block refill of both the
instruction and data caches with variable block sizes.
鈥?Supports concurrent refill and execution of instructions.
鈥?Partial word stores executed as read-modify-write.
鈥?6 external interrupt inputs, 2 software interrupts, with
single cycle latency to exception handler routine.
鈥?Flexible multiprocessing support on chip with no impact on
uniprocessor designs.
鈥?A single chip integrating the R3000 CPU and R3010 FPA
execution units, using the R3000A pinout.
鈥?Software compatible with R3000, R2000 CPUs and R3010,
R2010 FPAs.
鈥?TLB disable feature allowing a simple memory model for
Embedded Applications.
鈥?Programmable Tag bus width allowing reduced cost cache.
鈥?Hardware Support of Single- and Double-Precision Float-
ing Point Operations that include Add, Subtract, Multiply,
Divide, Comparisons, and Conversions.
鈥?Sustained Floating Point Performance of 11 MFlops single
precision LINPACK and 7.3MFLOPS double precision
鈥?Supports Full Conformance With IEEE 754-1985 Floating
Point Specification
鈥?64-bit FP operation using sixteen 64-bit data registers
鈥?Military product compliant to MIL-STD 833, class B
IDT79R3500 PROCESSOR
CONTROL
Master Pipeline/Bus Control
FPA
CPO
(System Control Coprocessor)
CPU
FPA Registers
Exponent Add Unit
FPA Divide Unit
FPA Multiply Unit
Exception/Control
Registers
Memory
Management
Unit Registers
Translation
Lookaside
Buffer
(64 entries)
Virtual Page Number/
Virtual Address
General Registers
(32x32)
ALU
Local
Control
Logic
Shifter
Integer
Multiplier/Divider
Address Adder
PC Increment/Mux
TAG (20+4)
ADDRESS (18)
The IDT logo is a registered trademark and RISCore, CEMOS are trademarks of Integrated Device Technology, Inc.
Data (32+4)
2871 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏 1992 Integrated Device Technology, Inc.
OCTOBER 1992
DSC-9054/3
5.3

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