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2001 Integrated Device Technology, Inc.
QRLWSLUFVH'
DPI
Transmit
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8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for network
side of SwitchStar DSLAM designs where full header access
is needed
Supports VPI Tunneling
Supports both UNI and NNI formats
Accounting functionality counts the number of cells on a
per VC basis
8-bit UTOPIA Level 1 Tx and Rx interfaces
Supports UTOPIA Level 1 cell mode operation
4-bit DPI Tx and Rx interfaces
DPI interface supports cell sizes from 52 to 56 bytes for
applications requiring a TAG
DPI interface operates up to 66MHz
In-Stream鈩?(In-band) programming for configuration of the
77V012, PHY and external search SRAM
Supports up to 8K active connections with an external 128K
x 32 SRAM. Up to 16K connections are supported in a 256K
x 32 SRAM
Inserts new ATM cell header and up to four bytes of TAG in
receive direction, and removes TAG from cell header in
transmit direction
Utility bus interface for programming PHY devices
Single +3.3V 鹵 0.3V power supply required
Inputs are +5.0V tolerant
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
WVL/ VHUXWDH)
WVL/ VHUXWDH)
WVL/ VHUXWDH)
WVL/ VHUXWDH)
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The IDT77V012 provides full header translation functionality along
with Data Path Interface (DPI) to UTOPIA Level 1 translation for switch
and DSLAM designs using the IDT SwitchStar. The address search and
replacement algorithm is performed using a VPI Tunneling or Full
Header format on 8, 12, 24, 28 or 32-bits of the header. This added flex-
ibility makes it suitable for both UNI and NNI formats. External memory
is required to perform the header translation (receive direction only),
which will support up to 16K connections using a 256K x 32 SRAM. The
new header, which is obtained as a result of the search, can be used to
overwrite the existing cell header in the receive path. A four byte TAG
can also be added to aid in routing cells.
The 77V012 also contains cell counters in the transmit and receive
direction. The counters can be used to provide detailed per VC
accounting information for a particular port.
Other features include In-Stream鈩?programming, which can be
utilized on either the DPI or UTOPIA interfaces, a Utility Bus interface for
accessing registers in the PHY device, and an interface for an
EEPROM.
5347drw01
March 26, 2001
DSC 5347/7