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IDT74SSTV16857PAG Datasheet

  • IDT74SSTV16857PAG

  • 14-BIT REGISTERED BUFFER WITH SSTL I/O

  • 6頁

  • IDT

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IDT74SSTV16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
INDUSTRIAL TEMPERATURE RANGE
14-BIT REGISTERED
BUFFER WITH SSTL I/O
IDT74SSTV16857
FEATURES:
鈥?/div>
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2.3V to 2.7V Operation
SSTL_2 Class II style data inputs/outputs
Differential CLK input
RESET
control compatible with LVCMOS levels
Flow-through architecture for optimum PCB design
Drive up to equivalent of 14 SDRAM loads
Latch-up performance exceeds 100mA
ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
鈥?Available in TSSOP package
DESCRIPTION:
The SSTV16857 is a 14-bit registered buffer designed for 2.3V-2.7V
V
DD
and supports low standby operation. All data inputs and outputs are
SSTL_2 level compatible with JEDEC standard for SSTL_2.
RESET
is an LVCMOS input since it must operate predictably during the
power-up phase.
RESET,
which can be operated independent of CLK and
CLK,
must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET,
when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of
RESET.
APPLICATIONS:
鈥?Ideally suited for DIMM DDR registered applications
FUNCTIONAL BLOCK DIAGRAM
RESET
34
CK
CK
38
39
V
REF
35
D1
48
1D
1
C1
R
Q1
TO 13 OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
c
2003 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MAY 2003
DSC-5737/5

IDT74SSTV16857PAG 產(chǎn)品屬性

  • IDT74SSTV16857

  • 39

  • 集成電路 (IC)

  • 邏輯 - 專用邏輯

  • 74SSTV

  • 寄存緩沖器，帶 SSTL_2 輸入和輸出

  • 2.3 V ~ 2.7 V

  • 14

  • 0°C ~ 70°C

  • 表面貼裝

  • 48-TFSOP（0.240"，6.10mm 寬）

  • 48-TSSOP

  • 管件

  • 74SSTV16857PAG800-1698800-1698-5800-1698-ND

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