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IDT74LVCH32373ABF Datasheet

  • IDT74LVCH32373ABF

  • LATCH|QUAD|8-BIT|LVC-CMOS|BGA|96PIN|PLASTIC

  • 7頁

  • ETC

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IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVCH32373A
3.3V CMOS 32-BIT
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
FEATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Typical t
SK
(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.8mm pitch LFBGA package, 96 balls
Extended commercial range of -40擄C to +85擄C
V
CC
= 3.3V 鹵0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4碌 W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
DESCRIPTION:
The LVCH32373A 32-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal
for temporary storage of data. The device can be used for implementing
memory address latches, I/O ports, and bus drivers. The Output Enable
and Latch Enable controls are organized to operate each device as four 8-
bit latches, two 16-bit latches, or one 32-bit latch. Flow-through organization
of signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
All pins of the LVCH32373A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
The LVCH32373A has been designed with a 鹵24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH32373A has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
Drive Features for LVCH32373A:
鈥?Balanced Output Drivers: 鹵24mA
鈥?Reduced system switching noise
APPLICATIONS:
鈥?5V and 3.3V mixed voltage systems
鈥?Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
A3
3
OE
J3
1
LE
A4
3
LE
J4
D
1
A5
D
A2
3
D
1
J5
D
J2
C
1
Q
1
C
3
Q
1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
2
OE
H3
4
OE
T3
2
LE
H4
4
LE
T4
2
D
1
E5
D
E2
4
D
1
N5
D
N2
C
2
Q
1
C
4
Q
1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
2000
Integrated Device Technology, Inc.
JANUARY 2000
DSC-4765/-

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