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IDT74LVCH16901APA Datasheet

  • IDT74LVCH16901APA

  • BUS TRANSCEIVER|SINGLE|18-BIT|LVC-CMOS|TSSOP|64PIN|PLASTIC

  • 145.51KB

  • 12頁

  • ETC

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IDT74LVCH16901A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER WITH PAR-
ITY GENERATORS/CHECKERS,
BUS-HOLD, 5V TOLERANT I/O
FEATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.50mm pitch TSSOP package
Extended commercial range of -40擄C to +85擄C
V
CC
= 3.3V 鹵0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4碌 W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVCH16901A
CMOS technology. The LVCH16901A is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses
in either direction.
The LVCH16901A features independent clock (CLKAB or CLKBA),
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or
CLKENBA)
inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA and
ERRB)
out-
puts for checking parity. The direction of data flow is controlled by
OEAB
and
OEBA.
When
SEL
is low, the parity functions are enabled. When
SEL
is high, the parity functions are disabled and the device acts as an 18-bit
registered transceiver. Inputs can be driven from either 3.3V or 5V
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
The LVCH16901A has been designed with a 鹵24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16901A has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
Drive Features for LVCH16901A:
鈥?High Output Drivers: 鹵24mA
鈥?Reduced system switching noise
APPLICATIONS:
鈥?5V and 3.3V mixed voltage systems
鈥?Data communication and telecommunication systems
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
FUNCTIONAL BLOCK DIAGRAM
LEAB
1
CLKENAB
2
CLKENAB
2
1
32
3
30
2
CLKAB
OEAB
35
OEBA
1
A
1
-
1
A
8
1
APAR
1
ERRB
2
A
1
-
2
A
8
2
APAR
2
ERRB
28
36
5
61
18
A-Port
Parity
Generate
and
Check
B Data
18-Bit
Storage
18
Q
A
B-Port
Parity
Generate
and
Check
A Data
18
29
60
4
1
B
1
-
1
B
8
1
BPAR
1
ERRA
2
B
1
-
2
A
8
37
2
BPAR
2
ERRA
18
Q
B
18-Bit
Storage
ODD/EVEN
SEL
34
31
62
CLKBA
1
CLKENBA
2
CLKENBA
2
64
33
63
LEBA
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
2000 Integrated Device Technology, Inc.
JUNE 2000
DSC-5412/-

IDT74LVCH16901APA相關(guān)型號(hào)PDF文件下載

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