IDT74LVC574A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS OCTAL
EDGE-TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
鈥?0.5 MICRON CMOS Technology
鈥?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?CMOS power levels (0.4碌 W typ. static)
碌
鈥?Rail-to-rail output swing for increased noise margin
鈥?All inputs, outputs, and I/O are 5V tolerant
鈥?Supports hot insertion
鈥?Available in SOIC, SSOP, QSOP, and TSSOP packages
IDT74LVC574A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
鈥?High Output Drivers: 鹵24mA
鈥?Reduced system switching noise
APPLICATIONS:
鈥?5V and 3.3V mixed voltage systems
鈥?Data communication and telecommunication systems
The LVC574A octal edge-triggered D-type flip-flop is built using ad-
vanced dual-metal CMOS technology. The device features 3-state outputs
designed specifically for driving highly capacitive or relatively low-imped-
ance loads. The LVC574A is particularly suitable for implementing buffer
registers, input-output (I/O) ports, bidirectional bus drivers, and working
registers.
On the positive transition of the clock (CLK) input, the Q outputs are set
to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly.
OE
does not affect the internal operations of the flip-flops.
Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
The LVC574A has been designed with a 鹵24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
FUNCTIONAL BLOCK DIAGRAM
OE
1
CLK
11
C
1
1
D
2
1
D
19
1
Q
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 1999 Integrated Device Technology, Inc.
MAY 1999
DSC-4679/1
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