鈥?/div>
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
Extended commercial range of -40擄C to +85擄C
V
CC
= 3.3V 鹵0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4碌 W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
DESCRIPTION:
The LVC16374A 16-bit edge-triggered D-type flip-flop is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The Output Enable (OE) and clock (CLK) controls are organized
to operate this device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout.
All inputs are designed with hysteresis for improved noise margin.
All pins of the LVC16374A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
The LVC16374A has been designed with a 鹵24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Drive Features for LVC16374A:
鈥?High Output Drivers: 鹵24mA
鈥?Reduced system switching noise
APPLICATIONS:
鈥?5V and 3.3V mixed voltage systems
鈥?Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
2
OE
24
48
1
CLK
47
2
CLK
25
1
D
1
D
2
2
D
1
36
D
13
C
1
Q
1
C
2
Q
1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4752/1