Integrated Device Technology, Inc.
鈥?/div>
Typical t
SK
(o) (Output Skew) < 250ps
鈥?ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
鈥?Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
鈥?Extended commercial range of -40擄C to +85擄C
鈥?V
CC
= 3.3V
鹵0.3V,
Normal Range or
V
CC
= 2.7 to 3.6V, Extended Range
鈥?CMOS power levels (0.4碌W typ. static)
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Low Ground Bounce (0.3V typ.)
鈥?Inputs (except I/O) can be driven by 3.3V or 5V
components
DESCRIPTION:
The FCT163501/A/C 18-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power 18-bit registered bus transceivers
combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each
direction is controlled by output-enable (OEAB and
OEBA
),
latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transpar-
ent mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic level.
If LEAB is LOW, the A bus data is stored in the latch/flip-flop
on the LOW-to-HIGH transition of CLKAB. OEAB performs
the output enable function on the B port. Data flow from B port
to A port is similiar but requires using
OEBA
, LEBA and
CLKBA. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT163501/A/C have series current limiting resistors.
These offer low ground bounce, minimal undershoot, and
controlled output fall times-reducing the need for external
series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
A
1
D
C
B
1
D
C
D
C
D
TO 17 OTHER CHANNELS
2776 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
漏1996
Integrated Device Technology, Inc.
AUGUST 1996
8.6
DSC-2776/4
1