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IDT74FCT162701TPV Datasheet

  • IDT74FCT162701TPV

  • Read/Write Buffer

  • 8頁(yè)

  • ETC

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IDT74FCT162701T/AT
FAST CMOS 18-BIT READ/WRITE BUFFER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 18-BIT
READ/WRITE BUFFER
IDT74FCT162701T/AT
FEATURES:
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0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
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1碌A(chǔ) (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
Balanced Output Drivers (鹵24mA)
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25擄C
Ideal for new generation x86 write-back cache solutions
Suitable for modular x86 architectures
Four deep write FIFO
Latch in read path
Synchronous FIFO reset
Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT162701T is an 18-bit Read/Write buffer with a four deep FIFO and
a read-back latch. It can be used as a read/write buffer between a CPU and
memory or to interface a high-speed bus and a slow peripheral. The A-to-B
(write) path has a four deep FIFO for pipelined operations. The FIFO can be
reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read)
path has a latch. A high on LE, allows data to flow transparently from B-to-A.
A low on LE allows the data to be latched on the falling edge of LE.
The FCT162701T has a balanced output drive with series termination.
This provides low ground bounce, minimal undershoot and controlled output
edge rates.
FUNCTIONAL BLOCK DIAGRAM
A
1-18
18
OEB A
RESE T
CLK
W CE
RCE
FF
FIFO
(4 deep)
LATCH
LE
OEA B
18
B
1-18
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-2915/1

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