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IDT74ALVCH162820PA Datasheet

  • IDT74ALVCH162820PA

  • 3.3V CMOS 10-BIT FLIP FLOP WITH DUAL OUTPUTS

  • 6頁

  • IDT

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IDT74ALVCH162820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 10-BIT FLIP-
FLOP WITH DUAL OUTPUTS
IDT74ALVCH162820
鈥?0.5 MICRON CMOS Technology
鈥?Typical t
SK(o)
(Output Skew) < 250ps
鈥?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?V
CC
= 2.5V 鹵 0.2V
鈥?CMOS power levels (0.4碌 W typ. static)
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Available in TSSOP package
FEATURES:
DESCRIPTION:
This 10-bit flip-flop is built using advanced dual metal CMOS technology.
The ALVCH162820 is an edge-triggered D-type flip-flop. On the positive
transition of the clock (CLK) input, the device provides true data at the Q
outputs.
A buffered output-enable (OE) input can be used to place the ten outputs
in either a normal logic state (high or low logic level) or a high-impedance
state. In the high impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without the need for interface or pullup
components.
OE
input does not affect the internal operation of the flip-flops.
Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
The ALVCH162820 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive 鹵12mA at the designated threshold
levels.
The ALVCH162820 has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
鈥?Balanced Output Drivers: 鹵12mA
鈥?Low switching noise
APPLICATIONS:
鈥?SDRAM Modules
鈥?PC Motherboards
鈥?Workstations
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
2
OE
28
CLK
56
2
1
Q
1
C
1
D
1
55
3
1
Q
2
D
1
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4497/2

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