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IDT72V72100 Datasheet

  • IDT72V72100

  • 3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO

  • 42頁

  • IDT

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3.3 VOLT HIGH-DENSITY SUPERSYNC II鈩?72-BIT FIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
IDT72V7230, IDT72V7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
IDT72V7290, IDT72V72100
FEATURES:
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Choose among the following memory organizations:
IDT72V7230
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512 x 72
IDT72V7240
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1,024 x 72
IDT72V7250
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2,048 x 72
IDT72V7260
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4,096 x 72
IDT72V7270
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8,192 x 72
IDT72V7280
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16,384 x 72
IDT72V7290
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32,768 x 72
IDT72V72100
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65,536 x 72
100 MHz operation (10 ns read/write cycle time)
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable word representation
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
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Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Asynchronous operation of Output Enable,
OE
Read Chip Select (
RCS
) on Read Side
Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
Features JTAG (Boundary Scan)
High-performance submicron CMOS technology
Industrial temperature range (鈥?0擄C to +85擄C) is available
擄
擄
FUNCTIONAL BLOCK DIAGRAM
D
0
-D
n
(x72, x36 or x18)
WEN
WCLK
LD
SEN
SCLK
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
512 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
FLAG
LOGIC
READ POINTER
BE
IP
BM
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
JTAG
CONTROL
(BOUNDARY SCAN)
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
RCS
Q
0
-Q
n
(x72, x36 or x18)
4680 drw01
OE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
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2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DECEMBER 2003
DSC-4680/9

IDT72V72100相關(guān)型號PDF文件下載

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  • 英文版
    HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
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    HIGH-SPEED 128K x 8 DUAL-PORT STATIC RAM
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    HIGH-SPEED 128K x 8 DUAL-PORT STATIC RAM
    IDT [Integrated...
  • 英文版
    HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
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  • 英文版
    HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
    IDT [Integrated...
  • 英文版
    HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
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  • 英文版
    HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
    IDT [Integrated...
  • 英文版
    HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
    IDT
  • 英文版
    HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
    IDT [Integrated...
  • 英文版
    HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
    IDT
  • 英文版
    HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
    IDT [Integrated...
  • 英文版
    x16 Dual-Port SRAM
    IDT
  • 英文版
    HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM
    IDT
  • 英文版
    HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM
    IDT [Integrated...
  • 英文版
    HIGH-SPEED 32K x 18 DUAL-PORT STATIC RAM
    IDT
  • 英文版
    HIGH-SPEED 2K x 8 FourPort STATIC RAM
    IDT
  • 英文版
    HIGH-SPEED 2K x 8 FourPort STATIC RAM
    IDT [Integrated...
  • 英文版
    HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM
    IDT

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