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IDT72V3654 Datasheet

  • IDT72V3654

  • 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 ...

  • 37頁

  • IDT

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3.3 VOLT CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT72V3654
IDT72V3664
IDT72V3674
FEATURES
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Memory storage capacity:
IDT72V3654 鈥?2,048 x 36 x 2
IDT72V3664 鈥?4,096 x 36 x 2
IDT72V3674 鈥?8,192 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using
EFA, EFB, FFA,
and
FFB
flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
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Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723654/723664/723674
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644
Industrial temperature range (鈥?0擄C to +85擄C) is available
擄
擄
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Output Bus-
Matching
Input
Register
36
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
36
Output
Register
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
Port-A
Control
Logic
36
FIFO1,
Mail1
Reset
Logic
36
Write
Pointer
Read
Pointer
Status Flag
Logic
EFB/ORB
AEB
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A
0
-A
35
EFA/ORA
AEA
FIFO1
Programmable Flag
Offset Registers
13
FIFO2
Timing
Mode
FWFT
B
0
-B
35
Status Flag
Logic
Read
Pointer
Write
Pointer
36
FFB/IRB
AFB
36
RT1
RTM
RT2
Output
Register
Input Bus-
Matching
36
2,048 x 36
4,096 x 36
8,192 x 36
Mail 2
Register
36
Input
Register
FIFO1 and
FIFO2
Retransmit
Logic
RAM ARRAY
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
Port-B
Control
Logic
MBF2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4664 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
錚?/div>
2003
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-4664/4

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