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IDT72V3643L10PF Datasheet

  • IDT72V3643L10PF

  • 3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING 256 x 36, 512 x 36,...

  • 28頁

  • IDT

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3.3 VOLT CMOS SyncFIFO
TM
WITH BUS-MATCHING
256 x 36, 512 x 36,
1,024 x 36
.EATURES:
鈥?/div>
IDT72V3623
IDT72V3633
IDT72V3643
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Memory storage capacity:
IDT72V3623鈥?56 x 36
IDT72V3633鈥?12 x 36
IDT72V3643鈥?,024 x 36
Clock frequencies up to 100 MHz (6.5 ns access time)
Clocked FIFO buffering data from Port A to Port B
IDT Standard timing (using
EF
and
FF)
or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Big- or Little-Endian format for word and byte bus sizes
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723623/723633/723643
擄
擄
Industrial temperature range (鈥?0擄C to +85擄C) is available
.UNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Port-A
Control
Logic
CLKA
CSA
W/RA
ENA
MBA
RS1
RS2
PRS
Bus-
Matching
Input
Register
Output
Register
FIFO1
Mail1,
Mail2,
Reset
Logic
36
36
RAM ARRAY
36
256 x 36
512 x 36
1,024 x 36
36
A
0
-A
35
Write
Pointer
Read
Pointer
B
0
-B
35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
36
36
SPM
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
10
Timing
Mode
Port-B
Control
Logic
Mail 2
Register
MBF2
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4662 drw01
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
錚?/div>
2001
AUGUST 2001
DSC-4662/3
1
Integrated Device Technology, Inc. All rights reserved. Product specifications sunject to change without notice.

IDT72V3643L10PF 產(chǎn)品屬性

  • 72

  • 集成電路 (IC)

  • 邏輯 - FIFO

  • 72V

  • 異步，同步

  • 36.8K（1K x 36）

  • 100MHz

  • 10ns

  • 3 V ~ 3.6 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 128-LQFP

  • 128-TQFP（14x20）

  • 托盤

  • 72V3643L10PF

IDT72V3643L10PF相關(guān)型號PDF文件下載

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