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IDT72V281 Datasheet

  • IDT72V281

  • 3.3 VOLT CMOS SuperSync FIFO?

  • IDT

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3.3 VOLT CMOS SuperSync FIFO鈩?/div>
65,536 x 9
131,072 x 9
.EATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
IDT72V281
IDT72V291
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Choose among the following memory organizations:
IDT72V281
65,536 x 9
IDT72V291
131,072 x 9
Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable
settings
Retransmit operation with fixed, low first word data
latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial Temperature Range (-40擄C to + 85擄C) is available
DESCRIPTION:
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
鈥?/div>
The limitation of the frequency of one clock input with respect to the other has
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
鈥?/div>
The period required by the retransmit operation is now fixed and short.
鈥?/div>
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
.UNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
8
LD SEN
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
WRITE CONTROL
LOGIC
RAM ARRAY
65,536 x 9
131,072 x 9
FLAG
LOGIC
WRITE POINTER
READ POINTER
OUTPUT REGISTER
MRS
PRS
READ
CONTROL
LOGIC
RT
RESET
LOGIC
RCLK
REN
OE
Q
0
-Q
8
4513 drw 01
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
錚?/div>
2001
Integrated Device Technology, Inc.
APRIL 2001
DSC-4513/1

IDT72V281 PDF文件相關(guān)型號(hào)

IDT72V281,IDT72V281L10PF,IDT72V281L10PFI,IDT72V281L10TF,IDT72V281L10TFI,IDT72V281L15PF,IDT72V281L15PFI,IDT72V281L15TF,IDT72V281L15TFI,IDT72V281L20PF,IDT72V281L20PFI,IDT72V281L20TF,IDT72V281L20TFI,IDT72V291,IDT72V2911L15PF,IDT72V291L15TFI

IDT72V281相關(guān)型號(hào)PDF文件下載

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