鈥?/div>
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (鈥?0擄C to +85擄C) is available
擄
擄
DESCRIPTION:
The IDT723623/723633/723643 are monolithic, high-speed, low-power,
CMOS unidirectional Synchronous (clocked) FIFO memories which support
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.
.UNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Port-A
Control
Logic
CLKA
CSA
W/RA
ENA
MBA
RS1
RS2
PRS
Bus-
Matching
Input
Register
Output
Register
FIFO1
Mail1,
Mail2,
Reset
Logic
36
36
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
36
36
A
0
-A
35
Write
Pointer
Read
Pointer
B
0
-B
35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
36
36
SPM
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
10
Timing
Mode
Port-B
Control
Logic
Mail 2
Register
MBF2
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
3269 drw01
COMMERCIAL TEMPERATURE RANGE
1
錚?/div>
2001 Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
AUGUST 2001
DSC-3269/2
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