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IDT723626 Datasheet

  • IDT723626

  • CMOS TRIPLE BUS SyncFIFO?

  • 563.63KB

  • IDT

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CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2
1,024 x 36 x 2
FEATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
IDT723626
IDT723636
IDT723646
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Memory storage capacity:
IDT723626 鈥?256 x 36 x 2
IDT723636 鈥?512 x 36 x 2
IDT723646 鈥?1,024 x 36 x 2
Clock frequencies up to 83 MHz (8ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using
EFA, EFB, FFA,
and
FFC
flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
鈥?/div>
鈥?/div>
鈥?/div>
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (鈥?0擄C to +85擄C) is available
擄
擄
DESCRIPTION:
The IDT723626/723636/723646 is a monolithic, high-speed, low-
power, CMOS Triple Bus synchronous (clocked) FIFO memory which
supports clock frequencies up to 83 MHz and has read access times as fast as
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Output Bus-
Matching
Input
Register
Output
Register
Port-A
Control
Logic
18
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
B
0
-B
17
36
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
36
FIFO1,
Mail1
Reset
Logic
36
Write
Pointer
Read
Pointer
Status Flag
Logic
Port-B
Control
Logic
CLKB
RENB
CSB
MBB
SIZEB
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A
0
-A
35
EFA/ORA
AEA
FIFO1
EFB/ORB
AEB
Common
Port
Control
Logic
(B and C)
Programmable Flag
Offset Registers
10
FIFO2
Timing
Mode
BE
Status Flag
Logic
Read
Pointer
Write
Pointer
FIFO2,
Mail2
Reset
Logic
Input Bus-
Matching
Input
Register
18
FWFT
FFC/IRC
AFC
MRS2
PRS2
36
Output
Register
36
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
36
C
0
-C
17
CLKC
WENC
MBC
SIZEC
Mail 2
Register
MBF2
Port-C
Control
Logic
3271 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
漏
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2001
DSC-3271/3

IDT723626 PDF文件相關(guān)型號(hào)

IDT723626,IDT723626L12PF,IDT723626L15PF,IDT723636,IDT723636L12PF,IDT723636L15PF,IDT723646,IDT723646L12PF,IDT723646L15PF

IDT723626相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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