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IDT723613L15PQFI Datasheet

  • IDT723613L15PQFI

  • CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 3...

  • 26頁

  • IDT

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CMOS CLOCKED FIFO WITH
BUS-MATCHING AND
BYTE SWAPPING 64 x 36
FEATURES:
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IDT723613
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Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
64 x 36 storage capacity FIFO buffering data from Port A to
Port B
Mailbox bypass registers in each direction
Dynamic Port B bus sizing of 36 bits (long word), 18-bits (word),
and 9 bits (byte)
Selection of Big- or Little-Endian format for word and byte bus
sizes
Three modes of byte-order swapping on Port B
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
FF, AF
flags synchronized by CLKA
EF, AE
flags synchronized by CLKB
Passive parity checking on each Port
Parity Generation can be selected for each Port
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Supports clock frequencies up to 67 MHz
Fast access times of 10 ns
Available in 132-pin quad flatpack (PQFP) or space-saving
120-pin thin quad flatpack (TQFP)
Industrial temperature range (鈥?0擄C to +85擄C) is available
擄
擄
DESCRIPTION:
The IDT723613 is a monolithic, high-speed, low-power, CMOS synchro-
nous (clocked) FIFO memory which supports clock frequencies up to 67 MHz
and has read-access times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO
buffers data from port A to port B. The FIFO has flags to indicate empty and full
conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty
(AE), to indicate when a selected number of words is stored in memory. FIFO
data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of
big- or Little-Endian configurations. Three modes of byte-order swapping are
possible with any bus-size selection. Communication between each port can
bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored. Parity is checked passively
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Parity
Gen/Check
MBF1
PEFB
PGB
Bus-Matching and
Output
Byte Swapping
Register
RST
ODD/
EVEN
Mail 1
Register
Parity
Generation
Input
Register
RAM ARRAY
64 x 36
Output
Register
Device
Control
36
64 x 36
36
Write
Pointer
FF
AF
FIFO
Read
Pointer
B
0
- B
35
Status Flag
Logic
Programmable
Flag Offset
Registers
FS
0
FS
1
A
0
- A
35
PGA
PEFA
MBF2
Port-B
Port-B
Control
Control
Logic
Logic
Parity
Gen/Check
Mail 2
Register
3145 drw01
EF
AE
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
IDT and the IDT logo are registered trademarks of Integrated Device Technology Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
漏 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2002
DSC-3145/1

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